Focal plane arrays include a detector array and corresponding read-out integrated circuit. In the early days of imaging, the detector array and read-out integrated circuit were implemented on one monolithic integrated circuit and the active area was dominated by the detector photo diode array. With modern three-dimensional hybridization processes, such as bump bonding and copper pillars, the detector array can be implemented in a specialized process technology and the read-out integrated circuit can be implemented in a high-density commercial process. This enables the large area under the detector array to be used for higher integration readout circuitry, including an analog to digital converter per pixel.
One compatible detector array utilizes micro-bolometers as a variable resistor responsive to infrared. Another detector array technology is a strained-layer super lattice as a charge output photodiode where structures are formed by selective deposition of thin layers of different semiconductor materials one above the other in a stacked arrangement to create a plurality of heterojunctions in the vertical or stacking direction. Many current strained-layer super lattice sensors have a size of 256×256 or 256×320 pixels. It is expected that in the near term the size will increase to 512×512 pixels as the strained-layer super lattice fabrication process improves. Long term expectations are for 1920×1080 pixel imagers. As the technology scales up to 1920×1080 imagers with readouts of 120 frames per second, read-out solutions must be improved.
Two-dimensional arrays of per pixel analog to digital converters have been utilized. Very high dynamic range systems present several challenges to such systems. A dominant portion of the analog to digital converter area is consumed by the counter, which increases in size linearly with the dynamic range (number of bits). These fully independent analog to digital converters do not have a global input to enable “skimming” to remove a portion of the scene offset charge before the analog to digital converter, therefore requiring more bits. The single capacitor (and its single reset) is sized for the smallest least significant bit (LSB), which necessitates an integration time proportional to the larger dynamic range instead of an integration time proportional to the object of interest signal to noise ratio (SNR) required for object identification. These difficulties result in larger area, higher power consumption and slower frame rates.